[A+] [Engineering] 스탑워치 VHDL 설계
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작성일 22-02-22 12:38
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Download : [공학] 스탑워치 VHDL 설계.hwp
SW_B : in std_logic;
library ieee;
library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity stop is PORT( CLK : in std_logic; SW_A : in std_logic; SW_B : in std_logic; SW_C : in std_logic; SW_D : in std_logic;
signal SW_F_Q1, SW_F_Q2 : std_logic;
use ieee.std_logic_1164.all;
signal SW_E_Q1, SW_E_Q2 , DEC : std_logic;
SW_A : in std_logic;
architecture arc of D_Clock is
SW_C : in std_logic;
signal seg_data7, seg_data8 : std_logic_vector(7 downto 0);--sec
use ieee.std_logic_arith.all;
SW_D : in std_logic;
공학,스탑워치 VHDL 설계
[Engineering] 스탑워치 VHDL 설계
signal Min : integer range 0 to 59;
signal dot : std_logic_vector(7 downto 0);--dot display(0 or 80)
entity stop is
signal Mode : std_logic_vector(2 downto 0) := 000;
![[공학] 스탑워치 VHDL 설계-1781_05_.jpg](/prev/201309/%5B%EA%B3%B5%ED%95%99%5D%20%EC%8A%A4%ED%83%91%EC%9B%8C%EC%B9%98%20VHDL%20%EC%84%A4%EA%B3%84-1781_01_.jpg../prev/201309/%5B%EA%B3%B5%ED%95%99%5D%20%EC%8A%A4%ED%83%91%EC%9B%8C%EC%B9%98%20VHDL%20%EC%84%A4%EA%B3%84-1781_02_.jpg../prev/201309/%5B%EA%B3%B5%ED%95%99%5D%20%EC%8A%A4%ED%83%91%EC%9B%8C%EC%B9%98%20VHDL%20%EC%84%A4%EA%B3%84-1781_03_.jpg../prev/201309/%5B%EA%B3%B5%ED%95%99%5D%20%EC%8A%A4%ED%83%91%EC%9B%8C%EC%B9%98%20VHDL%20%EC%84%A4%EA%B3%84-1781_04_.jpg../prev/201309/%5B%EA%B3%B5%ED%95%99%5D%20%EC%8A%A4%ED%83%91%EC%9B%8C%EC%B9%98%20VHDL%20%EC%84%A4%EA%B3%84-1781_05_.jpg)
signal seg_data5, seg_data6 : std_logic_vector(7 downto 0);--Min
signal seg_data3, seg_data4 : std_logic_vector(7 downto 0);--Hour
PORT(
signal SW_C_Q1, SW_C_Q2 , INC : std_logic;
signal SW_D_Q1, SW_D_Q2 : std_logic;
signal cnt : integer range 0 to 999;
signal SW_B_Q1, SW_B_Q2 : std_logic;
레포트 > 공학,기술계열
signal Hour : integer range 0 to 23;
Download : [공학] 스탑워치 VHDL 설계.hwp( 97 )
CLK : in std_logic;
순서
signal SW_A_Q1, SW_A_Q2, GO : std_logic;
설명
signal Sec : integer range 0 to 59;
end D_Clock;
use ieee.std_logic_unsigned.all;
다.
